Compound semiconductor photodetectors and their arrays have been in high demand as photo-sensing devices for optical communications and spectroscopic systems or infrared cameras in a variety of applications in the fields of medicine, disaster prevention, and industrial inspection, because they have the sensitivity in the near-ultraviolet and near-infrared regions in which silicon photodetectors don't cover.
The photodiode, which comprises the semiconductor p-n junction, is simple in its operating principle and excellent at quantitative performance, however, detection limit of the entire photo-detection system is determined by the noise characteristics of electric amplifiers. Since only one pair of electron and hole is generated with one photon at most, this causes very small current output at weak incident light. Therefore, a photo-transistor has been developed for a compound semiconductor photodetector, which has an internal amplification function.
In the conventional study as disclosed in the following Document 1, optical response of several tens A/W in the 1.5 micron wavelength range is obtained in the response speed of several GHz to several tens GHz for a photodetector for high-speed optical communications when light is irradiated to a HEMT (High electrons Mobility Transistor).
Document 1: C. S. Choi, H. S. Kang, Woo-Young Choi, H. J. Kim, W. J. Choi, D. H. Kim, K. C. Jang, and K. S. Seo, “High Optical Responsively of InAlAs—InGaAs Metamorphic High-electrons Mobility Transistor on GaAs Substrate with Composite Channels”, IEEE Photonics Technology Letters vol. 15 No. 6 (2003) p. 846-p. 848
Moreover, as disclosed in the following Document 2, the structure in which slow holes are discharged preferentially has also been developed in order to improve the response speed of the device. However, when holes are discharged intentionally, there are some issues on reduced sensitivity and restrictions of the photo-sensitive area near the FET gate.
Document 2: JP-A H05-343732
Furthermore, the study to use a heterojunction bipolar transistor (HBT) as a heterojunction bipolar photo-transistor (HPT) has also been made since 1980s. In the HPT, electron current is injected into the base region from the emitter region until it acquires the recombination rate equal to the amount of injected holes as the base current, and the ratio between electrons and hole current is equivalent to the current amplification factor. In this case, it is important to obtain the high current amplification factor that a barrier to the electrons and holes exists at the boundary of the base and the wide bandgap emitter region, the barrier in the valence band to the hole is large enough, the transfer of the holes to the emitter region is impeded, and the height of the conduction band barrier to the electrons is lowered upon light irradiation.
Although HPT has an advantage of high gain with a simple structure, it is necessary to set up the base bias voltage through a high resistance element in order to make up the matrix switch for the pixel selection because the sensitivity to light will disappear if the base is set to a fixed voltage.
It is a common practice to take several seconds to several minutes in order to perform the accurate measurement in physical and chemical science. Moreover, integration time of 1/30 second per one visible frame is required for each pixel in an image sensor, which is comparatively long. Thus, a highly sensitive device with a structure feasible for high-density integration is more preferable than a high speed device for a large majority of applications except for the purpose of optical communication.
The present inventors have already disclosed the photo-FET, which combined a pin photodiode and a FET in the Document 3 (PCT/JP2007/052913). As for the photo-FET disclosed in this Document 3, an integration time and a large gain suitable for instrumentation measurement and image pick-up applications can be ensured by accumulating the holes intentionally in return for the reduction of the response time to tens of KHz. The structure of this device is briefly illustrated in FIG. 14. The channel layer 150 used as the current path between the source electrode 300 and the drain electrode 320 of the FET built on the semi-insulating substrate 100 functions as a cathode and photosensitive region of a photodiode. And the back gate 130, which comprises the semiconductors of reversed polarity with the channel layer 150, functions as an anode of the photodiode. The source electrode 300, the drain electrode 320, and the gate electrode 310 disposed between them are placed on the barrier layer formed on the channel layer 150. The gate electrode 310 is disposed on the surface-side-depletion-layer forming layer 210 to form a p-n junction gate further, and the depletion layer 340 is extended to the channel-layer area under this layer 210.
Document 3: International Publication (WO) No. 2007/094493
In the prior art, a focal plane array (FPA: Focal Plane Array) structure has been adopted in a compound semiconductor infrared image sensor in which a two-dimensional charge amplifier array of a silicon integration circuit and a compound semiconductor two-dimensional photodetector array are bonded together. However, FPA has a disadvantage that it requires a difficult process of bonding a thin-sliced pin photodetector array and a silicon amplifier array to dispose each element of read-out charge-amplifiers and pin photodetectors arranged in two dimensions. Moreover, there are some other issues such that a two-dimensional charge amplifier array becomes large scale in total and that the area of amplifiers assigned to each cell is restricted. This makes the advanced signal processing difficult.
On the other hand, in the structure shown in Document 3, the photo-FET array is also disclosed wherein a FET is formed in each cell. It allows the output of the selected cell to be cut off by turning the bias of the FET gate to negative. Therefore, read-out of the two dimensional pixels is enabled by selecting each column with a planar hybrid module using a one-dimensional charge amplifier array. Furthermore, while holes are injected inside the channel layer 150 from the back gate 130 as minority carriers under illumination, these holes are accumulated inside the channel 150 since the preferential barrier layer 160 to these holes is disposed. Responding to this, the amount of electrons equivalent to the number of the accumulated holes inside of the channel is induced to fulfill the charge neutrality conditions inside of the channel. In fact, the electrons induced in this photo-FET is injected from the source electrode 300 through the barrier layer 160 that is penetrable to the electron, and is discharged to the drain electrode 320 through the channel layer 150. In other words, 10,000 to 100,000 times as many electrons, which is equivalent to the sojourn time of the holes divided by the transit time of the electrons, run inside the channel layer 150 against one hole, and high amplification performance can be achieved, which could not be obtained with the conventional devices.
Furthermore, in the photo-FET indicated in Document 3, the electric current proportional to the amount of the excited holes can be acquired, and photoinduced current can be amplified for a wide range of the light intensity from femto-watt (fW) level to milli-watt (mW) level. Thus, high sensitivity and wide photosensitive spectra can be ensured with this photo-FET structure. Furthermore, it also becomes possible to add the addressing function of the two-dimensional matrix when the depletion layer 340 is controlled with the gate voltage applied to the gate electrode 310.
On the other hand, as shown in the following Document 4, in the monolithic optical IC in which the output of a pin photodiode is inter-connected to the gate of the FET, the bias circuits using resistors or such kinds are required to ensure both the gate-bias conditions for the optimum FET gain and the photodiode bias-voltage simultaneously. Moreover, second epitaxial growth is preferable to form FETs on the semi-insulating substrate and to form photodiodes with sufficiently thick photo-absorption layer on the same substrate.
Due to such complicated fabrication processes and design to ensure the optimum operating conditions, apparent advantage has not been recognized in the monolithic optical ICs over the hybrid case when individual FET and photodiode fabricated on the different substrates are interconnected with wire bonding techniques.
Document 4: JP-A H06-244452
As another conventional structure device shown in the following Document 5, a threshold voltage modulation image Sensor (VMIS) has been developed as the advanced type of the silicon CMOS image sensor. In this device, a highly sensitive photodetector can be realized by applying the output voltage of a photodiode as the back gate voltage of MOSFET through the p-channel well. However, this is the structure functional only with the lateral doping profile realized by the ion implantation technique, and it is hard to apply in the compound semiconductor device process technology using a semiconductor hetero-structure because the annealing process after ion implantation induces crystal defects and inter-mixing of the hetero-interfaces.
Document 5: JP A 2004-241487
On the other hand, in the photo-FET shown in the above Document 3, an FET and photodetector are integrated on the same substrate with a relatively simple fabrication process of etching and electrode formation only. And, a highly sensitive photodetector can be fabricated without losing the electronic characteristics of the laterally uniform compound semiconductor epitaxial layer.
When looking into the structure where the output of a photodiode is connected to the back gate of FET, it is also important to improve the performance of the photodiode because the noise generated in the photodiode part will be amplified in the FET part as it is. In the general classification of conventional photodiode, there are mesa type and planar type. With mesa type, a p-n junction is formed with crystal growth in advance, and then, a required device region is to be formed by etching. With planar type, impurities are selectively induced from the n-type epitaxial layer surface, and the part of the anode side is reversed to p-type. Although the mesa structure has an advantage in reducing the device size and floating capacitance, which is suitable for high-speed photodetectors, there is an issue of large surface leak current at the p-n junction exposed at the mesa sidewall. On the other hand, the planar type has an advantage of suppressed surface leak current since the p-n junction containing a photo-absorption layer is not exposed to the surface.
In general, the crystal surface has large crystal defect density as compared with the inside of a crystal. Therefore, the recombination current will become serious in case when the photo-absorption layer with a narrow bandgap is exposed to the surface and kept at the depletion condition. Therefore, dark current can be suppressed by forming the air-exposed p-n junction with the wide energy bandgap semiconductor by selective diffusion of impurities from the wide energy bandgap cap layer.
Also as for the mesa type photodiode, as shown in the following Documents 6 and 7, there are some inventions to suppress the dark current by selective impurity diffusion surrounding the whole mesa structure and the part of the wide bandgap semiconductor layer at the bottom of the mesa structure. The mesa structure is comprised of a photo-absorption layer with the narrow bandgap semiconductor layer on the wide bandgap semiconductor layer as in Document 6. Or, as shown in the following Document 7, the photo-absorption layer comprised with the narrow bandgap semiconductor layer is sandwiched with the wide bandgap semiconductors up and down.
Document 6: Kiyoshi OHNAKA, Minoru KUBO, and Jun SHIBATA, ‘A Low Dark Current InGaAs/InP pin Photodiode with Covered mesa Structure’, IEEE Transactions on electrons Devices, Vol. ED-34, No. 2, February 1987, p. 199-204
Document 7: U.S. Pat. No. 4,999,696, FIG. 1b 
It is sure that dark current can be suppressed if a Zn diffused layer is extended to the surface of a lower InP layer and if the p-n junction exposed to the surface is limited to the InP layer with wide bandgap energy. Moreover, as for the mesa structure, the cross talk between each element in the array type detector is also suppressed because the photo-absorption layer can also be separated physically for every one device.
Among such conventional prior art, there are various advantages over the other former devices in the photo-FET of shown in the previous Document 3. However, some issues on the design and processes have been still recognized. For example, in the photo-FET disclosed in this Document 3, the channel 150 of FET functions as the cathode of the photodiode, and the back gate 130 of FET functions as the anode of the photodiode, respectively, at the same time. And the source electrode 300 of FET and the anode potential of the photodiode, i.e., the electric potential of the back gate layer 130, are interconnected through the channel layer 150. Therefore, it is difficult to optimize the device configuration and operation conditions as an amplifier and also to optimize these as a photodiode, respectively. For example, bias voltage for the photodiode part is not controllable from the outside.
To be specific, it is desirable that the source electrode 300 and the drain electrode 320 be formed on a highly-doped, narrow bandgap n-type InGaAs layer, for example, in order to decrease the parasitic resistance as FET. On the other hand, the top surface should be a window material as a photodiode, for example, an InP or InAlGaAs layer, which is transparent for the wavelength band of the incident light since it is not desirable that a photo-sensitive surface is covered with a narrow bandgap material.
Moreover, since the channel layer 150 of the FET is shared with the cathode of the photodiode, there is a tendency that the photoinduced signal from the photodiode is not effectively transmitted to the FET. The cathode conductivity of the photodiode tends to reduce simultaneously when the carriers concentration of the channel is lowered for securing the normally-off conditions in order to suppress the dark current level. Therefore, there was a problem of the material design that the optimum range of the doping concentration of the channel layer 150 becomes narrow.
Furthermore, there is also another problem. It is desirable for the FET that the short channel FET structure, which shortened the distance between the source and the drain electrodes (300, 320), should obtain a high transconductance (gm) FET and should be driven with relatively low source drain voltage no more than 0.5V in order to suppress the dark current (the leakage current without illumination) induced by impact ionization. On the other hand, the applied bias voltage of more than 1 to 2V is usually desirable for the photodiode to extend its depletion layer to some extent and to drift the photoinduced carriers. However, since the photodiode is serially-cascaded to the source drain of the FET inside this photo-FET device, the voltage between the anode and cathode of the photodiode will be always set lower than the bias voltage between the source and drain of the FET. Therefore, it becomes the issue that neither the gain of the photo-FET nor the suppression of the dark current is sufficient. The depletion layer will not fully spread in the photodiode when the bias voltage of the FET is restricted to induce the range of the electric field where impact ionization will not take place.
Moreover, the gain of FET will drop in case the injected holes are recombined at the air-exposed mesa sidewall of the FET part constituting the photo-FET. The generation of minority carriers becomes serious at the air-exposed mesa sidewall of the photodiode part if a depletion layer exists in the narrow bandgap photo-absorption layer.
The present invention mainly aims to solve these issues of suppressing the dark current in the photodiode part and the reduction of gain in the FET part by providing the new photo-FET with the optimum design for the FET part and the photodiode part, respectively, and by enabling the application of independent bias voltage for each part.